10.07.25 | Vollzeit | Genève | JobLeads GmbH | CHF 80’000 - CHF 100’000 Communication protocols. In particular JESD204B. Wishbone, VME64x, and Intel Avalon, SPI, I2C; - Solid understanding of Digital Signal Processing (DSP) and Clock Domain Crossing (CDC) Techniques; - Experience in version control systems, specifically Git; - Knowledge of good practices for long-term programme
Später ansehen10.07.25 | Vollzeit | Genève | JobLeads GmbH | CHF 80’000 - CHF 100’000 Time signal processing. Your profile Skills - Experience with hardware description languages (HDL), especially System Verilog (Verilog and VHDL would be an asset); - Experience with Python; - Experience in the design of complex digital design systems, implemented using FPGAs; - Strong understanding
Später ansehen10.07.25 | Vollzeit | Genève | JobLeads GmbH | CHF 80’000 - CHF 100’000 Communication protocols. In particular JESD204B. Wishbone, VME64x, and Intel Avalon, SPI, I2C; - Solid understanding of Digital Signal Processing (DSP) and Clock Domain Crossing (CDC) Techniques; - Experience in version control systems, specifically Git; - Knowledge of good practices for long-term programme
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